1. Technical Field
The present disclosure relates to a complementary metal oxide semiconductor (hereinafter referred to as “CMOS”) image sensor and, more particularly, to a CMOS image sensor manufacturing method which can reduce current leakage and resistance generated during an active contact formation.
2. Description of Related Art
Typically, an image sensor converts optical images to electric signals. The types of image sensors are largely divided into a CCD (charge coupled device) type and a CMOS type. A CCD type image sensor comprises several MOS (metal oxide semiconductor) capacitors, closely positioned to one another, wherein electric charge carriers are transferred to or saved in the MOS capacitors. A CMOS type image sensor employs a CMOS technology (i.e., both a control circuit and a signal processing circuit are used as a peripheral circuit). According to the CMOS technology, the CMOS image sensor has as many MOS transistors as pixels and detects the outputs of the pixels using the MOS transistors. In other words, the CMOS image sensor adopts a switching method.
In recent years, to improve the photo-sensitivity of image sensors, various researches have been conducted. One of the intensively researched areas is a light-collecting technology. A CMOS image sensor may comprise photodiodes for detecting light and a CMOS logic circuit for generating data by converting the detected light into an electric signal. To achieve a high photo-sensitivity in the CMOS image sensor, the light-collecting technology has been developed toward increasing the ratio of the area of the photodiodes to the entire area of the image sensor.
In contrast to CCDs, CMOS type image sensors may be highly integrated. Particularly, a salicide formation process comprising a step of forming a salicide layer made of Ti or Co on gate electrodes and source/drain regions, may be performed for the image sensors employing a line width of less than 0.25 μm.
A prior art method for fabricating an image sensor may be described with reference to FIGS. 1a and 1b. As shown in FIG. 1a, an image sensor 10 includes a plurality of transistors 12, e.g., 12-1, 12-2, 12-3, and a photodiode 14. Each transistor 12 includes a gate 16, i.e., 16-1, 16-2, 16-3, and source/drain regions labeled as S/D in FIG. 1a. Also shown in FIG. 1a is an active region 18 defined between transistor 12-1 and photodiode 14. Active region 18 is connected to gate 16-2 of transistor 12-2.
Image sensor 10 may be formed on a semiconductor substrate. First, a field insulating layer is partially formed on the semiconductor substrate. A layer of gate oxide and is formed on areas separated by the field insulating layer and gate electrodes are formed on the layer of gate oxide. Photodiode 14 and S/D regions are formed by an ion implantation process. The semiconductor layer comprises a high concentration P++ and P type epitaxial layer. A metallic layer such as a Ti layer is then grown on the surface of the resulting structure with a thickness between 300 Å and 500 Å by a sputtering method.
A silicide is then formed through a rapid thermal process (hereinafter referred to as “RTP”) at a temperature about 730° C. and for about 20 minutes. The RTP is conducted in an N2 atmosphere, leading to the reaction of Si and Ti metals. As a result, a silicide layer made of TiSi2 is formed.
Optionally, a salicide formation process may then be performed. Because oxide does not react with Ti, the unreacted residues of the Ti may remain on the gate oxide layer. Thus, a predetermined cleaning process is required to remove the unreacted residues of the Ti. Subsequently, another RTP is conducted at a temperature about 850° C. to form the salicide layer. The RTP is conducted in a N2 atmosphere, resulting in the formation of the salicide layer. The formed salicide layer reduces resistance generated during the formation of a contact, such as a floating diffusion.
An interlayer dielectric layer is then formed to insulate an area between the gate electrode and a first metal contact layer. Next, the interlayer dielectric layer is selectively etched to make a contact area on the metallic layer. A pattern of the first metal contact layer is formed on the contact area.
As shown in FIG. 1a, two first metal contacts, 20-A and 20-B are formed on active region 18 and gate electrode 16-2, respectively. The prior art simultaneously makes the two first metal contacts 20-A and 20-B. However, as shown in FIG. 1b, active region 18 may be over-etched during the formation of contacts 20-A and 20-B. The over-etching of active region 18 damages the inside silicon substrate, and consequently, changes the amount of current leakage and the value of resistance.
U.S. Pat. No. 6,040,592 to Bart et al. discloses an image sensor having a well-to-substrate diode as a photodetector by utilizing a modem salicide process to manufacture the image sensor.
U.S. Pat. No. 6,495,434 to Howard E et al. discloses an imaging device formed as a CMOS semiconductor integrated circuit which includes a buried contact line between a floating diffusion region and a gate of a source follower output transistor.
U.S. Pat. No. 6,344,668 to Keisuke et al. discloses an image pickup element unit and peripheral circuits which are formed on a common semiconductor substrate. The image pickup element unit comprises sensors which converts incident lights into charges. The peripheral circuits comprise contact holes therein and transfer signals to external components via the contact holes.